1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for improving halo implants for semiconductor devices to improve performance.
2. Description of the Related Art
Semiconductor devices include transistors formed integrally with a substrate. Since the substrate is commonly used by many transistors and for components of a same transistor, current leakage may occur.
Referring to FIG. 1, a cross-sectional view of a semiconductor device is shown. Semiconductor device 10 includes a substrate 12, which is preferably a lightly doped crystalline material, such as silicon. In previous steps, which are known to those skilled in the art, a gate stack 14 is formed on substrate 12. Gate stack 14 includes a gate oxide 16 and a conductive material for a gate conductor 18, such as polysilicon. Gate stack 14 may include other layers as well, for example a silicide or other higher conductive material. Gate stack 14 is preferably protected from implantation by employing a nitride cap 20 and nitride spacers 22. Diffusion regions are formed in substrate 12 on opposite sides of gate stack 14. Dopants are implanted in theses regions by bombarding substrate 12 with the dopants. It is desirable to have the halo dopants penetrate below gate stack 14. This may be accomplished by permitting dopants to impact a surface 24 of substrate at angle of about 10-30 degrees. This permits dopants to penetrate below gate stack 14.
As described above, since dopant regions on both sides of the gate are relatively close, a halo implantation is performed prior to formation of sources and drains for transistors on substrate 12. Referring to FIG. 2, a field effect transistor 32 is shown. Transistor 32 includes gate stack 14 between two diffusion regions. The diffusion regions which are formed by the dopant implantation described above. The diffusion regions include a source 34 and a drain 36. Prior to formation of source 34 and drain 36, halo implant 38 is formed to reduce current leakage from source 34 and drain 36. Halo implants 38 include a conductivity opposite the conductivity of source 34 and drain 36.
Referring to FIG. 3, a semiconductor wafer 40 is shown. Wafer 40 includes a plurality of chips 42 formed thereon. Wafer 40 includes a notch 44 which is employed to provide a reference for semiconductor fabrication processes. Lines 46 are provided to indicate angles relative to notch 44. These angles include 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Detail 4 is indicated in FIG. 3. Detail 4 is magnified in FIGS. 4 and 5 and illustratively shows an orientation of gate conductors 18 along a chip 42.
As shown in FIG. 4, gate conductors 18 are arranged parallel to a direction of notch 44 (notch direction is illustratively indicated in FIG. 4). For conventional halo implant processes, implantation is directed at an angle (i.e. 10 degrees-30 degrees with respect to a normal to the surface of wafer 40) to implant under gate conductors 18. To get under the gate the implantation tool is aimed or directed perpendicular to the direction of gate conductors 18 (i.e. along the 270 degrees direction and the 90 degrees direction). This is in addition to the angle formed with a surface normal of the substrate (as shown in FIG.1). This means wafer 40 (FIG. 3) is rotated to these positions in a processing chamber to provide the implantation under gate conductors 18. In this way, dopants may be implanted under a portion of gate conductor 18.
As shown in FIG. 5, gate conductors 18 are oriented perpendicular to notch 44 (notch direction is illustratively indicated in FIG. 5). The perpendicular and parallel orientations shown in FIGS. 4 and 5 represent a highly desirable arrangement for gate conductors 18 since notch 44 is used to indicate direction for the fabrication process. Since gate conductors in FIG. 5 are rotated by 90 degrees, the implantation tool is now aimed in the 0 degrees direction and the 180 degrees.
Referring to FIG. 6, a top view of a gate conductor 18 with source 34 and drain 36 formed therein is shown. Arrows A are indicated only as a reference to illustratively show the direction of implantation of halo implant 38 (FIG. 2). In a conventional device, source 34 and drain 36 are counter-doped by the halo to a concentration of about 3D where D is a halo dose of between about 1.times.10.sup.12 to about 1.times.10.sup.13 atoms/cm.sup.2. Under gate conductor 18, a concentration of about D is provided in regions 50 and 52. These relatively high dopant concentrations are subject to high current leakage.
The dopant concentration (D) under gate conductors may be insufficient. Since, halo implant 38 does not extend far enough below gate conductors 18, a higher concentration of dopants (source/drain dopants) may not be sustainable without experiencing performance degradation. For example, a threshold voltage roll-off for the transistor may be increased and/or junction capacitance (between source 34 and drain 36) may be increased.
Therefore, a need exists for a method for implanting a higher halo dose under a gate which does not degrade performance. A further need exists for a method for forming a halo implant which provides reduced junction capacitance and reduced threshold voltage roll-off to improve semiconductor device performance.